1. Field of Invention
The present invention relates to a memory device and programming method thereof, and more particularly, to and Electrically Erasable and Programmable Read Only Memory (EEPROM) cell and programming method thereof.
2. Description of the Related Art
Electrically Erasable and Programmable Read Only Memory (EEPROM) serves for multiple data write/read/rapid erase operations, and the data stored therein stays after supplying power is off. Therefore, it is a versatile memory device that is broadly used in a personal computer and other electronic appliances.
A silicon nitride ROM is one of the common categories of EEPROM, whose structure is illustrated in FIG. 1. Referring to FIG. 1, the silicon nitride ROM comprises a stacking layer 108, formed by silicon oxide tunneling dielectric layer 102/silicon nitride charge trapping layer 104/silicon oxide tunneling dielectric layer 106 sequentially, disposed on a substrate 100, a gate conductive layer 110 over the stacking layer 108, and source/drain regions 112a and 112b disposed on two sides of the gate conductive layer 110 in the substrate 100. Applying a bias configuration to the source/drain region 112a and the gate conductive layer 110 to program the EEPROM cell, where electronic charges in the substrate 100 are injected to the area 114 of the charge trapping layer 104 adjacent to the source/drain region 112a via Channel Hot Electron Injection (CHEI) effect, and a bit is stored therein.JunO42004JunO42004 Similarly, the above bias configuration can be applied to the source/drain region 112b and the gate conductive layer 110 for another programming operation, such that electronic charges in the substrate 100 are injected to an area 116 of the charge trapping layer 104 adjacent of the source/drain region 112b via CHEI effect, and another bit is stored therein. In other words, with programming operations in different directions, electronic charges are respectively stored on two sides of the charge trapping layer 104, i.e. the silicon nitride EEPROM is a memory cell capable of two bits, namely 2 Bit/Cell.
However, if a bit is already stored in the area 114 or 116, when operating reverse read to the silicon nitride EEPROM cell, i.e. a reading direction is opposite to the programming direction, a 2nd-bit effect might occur. That is, the stored bit increases the potential barrier. Therefore a threshold voltage Vt of reading operation is increased, and further limiting a sensing window between the threshold voltages of the two bits stored on two sides of the charge trapping layer.
Besides, if operating one-side reading to the silicon nitride EEPROM, then the Vt level of the bit adjacent to the source/drain region 112b in FIG. 1 is affected.
Referring to FIG. 2A, it illustrates a transfer profile of the reading voltage and the threshold voltage level, where the horizontal axis represents reading voltage in volts, whereas the vertical axis represents threshold voltage level in volts. Moreover, the circle and square symbols in FIG. 2A respectively represent transfer profiles between the reading voltage and the threshold voltage for the right hand side and left hand side of the charge trapping layer. According to FIG. 2A, since the source/drain region on the right hand side is biased, a potential barrier of the bit stored on right hand side in the charge trapping layer is negatively affected, i.e. lowered, and thus an effective threshold voltage is lowered. Therefore, the threshold voltage level of the bit stored on right hand side in the charge trapping layer is lower than that of the bit stored on left hand side in the charge trapping layer.
Referring to FIG. 2B, which is similar to FIG. 2A, where a transfer profile between a reading voltage and a threshold voltage level is illustrated. What is different in FIG. 2B from FIG. 2A is an amount of electronic charges stored on two sides of the charge trapping layer, i.e. more electronic charges are stored in FIG. 2B than FIG. 2A. In FIG. 2B, more electrons are stored on two sides of the charge trapping layer, yet the effective threshold voltage is still affected by whether the adjacent source/drain regions are biased with voltage. That is, the bit stored on right hand side of the charge trapping layer is affected by the source/drain region with biased voltage on the right hand side, the effective threshold voltage is still lowered, which cannot be similar to that of the bit stored on left hand side of the charge trapping layer.